1. Field of the Invention
This invention relates to ATM (asynchronous transfer mode) testing technology. ATM testing is performed for the purpose of verifying the reliability of data transferred in ATM communications systems.
2. Description of Related Art
ATM testing is testing that is performed to detect whether or not data have been properly transmitted through a communications path. In such testing, the presence or absence of bit errors in the data and the presence or absence of cell rejection are detected. Cell rejection refers to the rejection of cell signals of low importance in order to protect data of high importance during network convergence. Cell rejection is adopted for the VBR (variable bit rate) services in B-ISDN (broadband aspects of Integrated Service Digital Network). The importance of cell signals is determined by the user.
ITU-T Recommendation I.363 defines AAL (ATM adaptation layer) protocols types 1 to 5 in the B-ISDN reference model. In communications in which the AAL type 5 protocol is adopted, the entire 48-byte information field in the ATM cell is used as payload.
In communications wherein the AAL type 5 protocol is adopted, two general ATM testing schemes are used, as described below.
The first of these testing schemes is specified in ITU-T Recommendation I.610. This scheme employs OAM (operation and maintenance) cells. In ITU-T Recommendation I.610, an OAM cell is referred to as a performance management cell. The OAM cell is an ATM cell that is different from the cells used to send user data, and hence is configured so that it can be distinguished from user cells. The transmitter stores sequence numbers and cyclic code in the OAM cells. The OAM cells are sent by the transmitter over the communications path with a fixed period. The receiver receives the OAM cells from the path, and inspects the sequence numbers and cyclic code in the OAM cells. Based on this inspection, the receiver detects the bit error occurrence rate and cell rejection rate.
The second testing scheme is a scheme that, using the ATM cells, sends control signals together with the user data. The control signals contain lengths (coding that indicates the packet length) and cyclic code. With this scheme, the AAL of the receiver, upon reception of a packet signal from a higher layer, adds a control signal to that packet signal. Next, by line-coding the packet signal and control signal, the AAL generates an ATM cell. This ATM cell is sent via a lower layer to the communications path. At the receiver end, the ATM cell received from the path is sent to an AAL via the lower layer. This AAL, after line-decoding the received ATM cell, extracts the control signal. The receiver, upon detecting a length anomaly, judges that this anomaly has been caused by a cell rejection. The receiver uses the cyclic code to detect the number of bit error occurrences.
These testing schemes, however, have the following shortcomings.
The first scheme detects only bit errors and cell rejections that occur between the transmitter and receiver. It cannot detect cell rejections and bit errors that occur prior to transmission from the transmitter, being unable, for example, to detect cell rejections and bit errors that arise prior to line coding. Hence this scheme suffers the shortcoming of being unable to detect cell rejections and bit errors from end to end.
The second scheme suffers the shortcoming of being unable to detect the number of cell rejections when ATM cells containing control signals are lost in the communications path.
An object of the present invention is to provide ATM testing technology wherewith bit errors and cell rejections can be detected from end to end, and wherewith the number of cell rejections can be detected even in cases where data containing control signals are lost in the communications path.
To attain this object, the ATM communications system according to the present invention comprises: a signal generator for generating packet signals by linking N data blocks that include user data and a specifier byte containing sequence number bits; a transmitter that receives the packet signals, generates control signals containing length information, generates Nxe2x88x921 ATM cells wherein one data block is accommodated in the payload, generates one ATM cell wherein one data block and one control signal are accommodated in the payload, and transmits all of the ATM cells over the communications path; and a receiver that receives the ATM cells from the communications path, detects the number of cell rejections using sequence number bits extracted from the specifier bytes in all of the ATM cells, and detects the number of bit error occurrences using length information extracted from the control signals.
In such a system as this, sequence number bits are accommodated in all of the ATM cells. Also, length information is accommodated in the N""th ATM cell. Accordingly, the bit errors and cell rejections can be detected from end to end, and the number of cell rejections can be detected even in cases where data containing control signals have been lost on the communications path.
The ATM testing method according to the present invention comprises: a generation step for generating packet signals by linking N data blocks that include user data and a specifier byte containing sequence number bits; a transmission step for generating control signals containing length information, generating Nxe2x88x921 ATM cells wherein one data block is accommodated in the payload, generating one ATM cell wherein one data block and one control signal are accommodated in the payload, and transmitting all of the ATM cells to the communications path; and a detection step for detecting the number of cell rejections using sequence number bits extracted from specifier bytes in ATM cells received from the communications path, and detecting the number of bit error occurrences using length information extracted from the control signals.
In such a system as this, sequence number bits are accommodated in all of the ATM cells and length information is accommodated in the N""th ATM cell. Accordingly, bit errors and cell rejections can be detected from end to end, and the number of cell rejections can be detected even in cases where data containing control signals have been lost on the communications path.